As microprocessors become less expensive and more powerful, the variety of applications where they are found is rapidly increasing. At the low end, microprocessors are now routinely found in home appliances, automobiles, cellular phones, cameras, network interfaces, personal digital assistants (PDAs), and more. At the high end, microprocessors are taking on tasks traditionally claimed by microcomputer systems, such as those based on the Intel 486 class of processors. This presents a problem.
Modern microprocessors, in order to do so many useful things, need to interface with a much larger number of different peripheral devices than those ever contemplated for, say, "simple" PCS. Usually, the specific operations performed by the peripheral devices are managed by control signals carried on bus lines. The signals can be generated by the control signal generator of the microprocessor's bus interface unit.
As one can imagine, there is no single industry standard for control signals. For example, the control signals for an "Intel" interface bears little in resemblance to those required for a "Motorola" interface. Because there is no single industry standard for a microprocessor bus, there is no single standard for control signals. However, in spirit, the buses are quite similar, since there really are only two operations, read and write.
Some devices conform to an ad-hoc standard defined many years ago by Intel for its 8-bit microprocessors. That is, they use asynchronous low-true (RD) and write (WR) strobes. More devices conform to the standard defined by Motorola for its microprocessors. The Motorola "standard" has a direction (RW) signal and a single low-true data strobe.
Control signals for memory devices show similar variations. Read-only, and simple static memories have an interface which is very similar to that used for Intel-style peripheral devices. However, dynamic memories typically have very different interfaces, and require a very different set of control signals. To make matters even worse, there are a number of variations on dynamic memory interfaces, e.g., normal DRAMs, extended-data-out DRAMs, bursting extended-data-out DRAMs, and so forth. Each protocol is different in some level of detail.
In the prior art, the usual way of dealing with this problem is as follows. First, the designer of the microprocessor develops a list of all the external devices that should be supported. Second, the designer develops a specification of how the control signals for the selected devices should work.
Now, the designer can build a complex ad-hoc controller that generates all of these control signals. In order to provide overall control, the designer also needs to come up with some kind of software loadable mode register. Last, the package needs to be equipped with dedicated external pins to carry the various control signals off the microprocessor chip. Having dedicated instead of general purpose pins is a less-than-satisfactory.
It is difficult to develop a specification for how the control signals should function. The interface standards for the external devices, such as memories and peripherals, are usually not formal standards. The requirements for these signals must be derived from a large number of data sheets of representative devices to determining the appropriate intersection/union of the representative specifications, and striking an appropriate compromise.
This is tedious and error-prone work. The work must be done very accurately because once the design is complete, the designer casts his or her logic into hard silicon where changes are difficult to make. Devices accidentally forgotten or erroneously specified could not be used. Also, if the actual devices operate slightly different than specified, adjusting the control signals accordingly is difficult. Even minor timing variations between like devices from different manufacturers may present a problem.
Even if the design was perfect, it would soon be out-of-date. New devices operating to different specifications would have to wait for the next redesign on the chip. The root cause of both of these problems is the same; present control signal generators include too many specific details of the supported devices and therefore require dedicated pins.
Therefore, it is desired to provide means which can be incorporated into a microprocessor for generation any number of arbitrary control signals that can operate a variety of external devices on general purpose external pins.